A storage system, in general, is configured to provide a logical volume which is created based on the RAID (Redundant Array of Independent Disks) group which is composed of plural storage devices. Recently, as a storage device, in addition to or in place of a HDD (Hard Disk Drive), a non-volatile semiconductor storage device which includes plural non-volatile memory chips as non-volatile semiconductor storage devices, has been adopted. PTL 1 discloses an FM, to be more specific, an NAND flash memory which includes plural flash memory (hereinafter, FM) chips, as a non-volatile semiconductor storage device.
A storage area of an NAND flash memory is divided into plural areas “blocks” each of which is an erase unit. In addition, each block is divided into plural areas “pages” each of which is a unit for read or write. Each page is composed of plural memory cells.
There are two kinds of memory cells which configure an NAND flash memory; an SLC (single Level Cell) type of memory cell which records 1 bit to one memory cell, and an MLC (Multi Level Cell) type of memory cell which records plural bits (in general 2 bits) to one memory cell. PTL 2 discloses a basic configuration and a control method of an NAND flash memory (hereinafter, referred to as MLC memory) which includes an MLC memory cell (MLC type of memory cell). In case of an MLC memory, data from the host apparatus will be written to an LSB (Least Significant Bit) page, or an MSB (Most Significant Bit) page.
In general, there is a problem in a MLC memory cell that it has a less program possible number of times (that is, fewer rewritable number of times) compared to an SLC memory cell (SLC type memory cell). In order to solve the problem, PTL 3 discloses a method to decrease a program number of times of an MLC memory cell by controlling data similar to the data pattern written to an LSB page, not to write to an MSB page.
In general, an MLC memory has a problem that a data error is likely to occur compared to an NAND flash memory (hereinafter, referred to as SLC memory) which includes an SLC memory cell. In order for an MLC memory to be able to use as an SLC memory which an error is unlikely to occur, PTL 4 discloses a method which data programs a reinforcement data to the programmed cell, and adjusts the threshold voltage to a safer condition. In addition, PTL 5 discloses a method on an MLC memory, while data is not being read and written; data executes a reprogram for the programmed cell, and adjusts the threshold voltage to a safer condition.
In general, an MLC memory is an LSB page which has a fast write performance in half of the pages out of plural pages in the block, and also has a feature of being an MSB page which has a slow write performance in the other half of the pages.
PLT 6 discloses a method to skip an MSB page, on a system which an MLC memory is applied to, in order to assign a write destination of the write data based on the write command from the host apparatus in which a fast response is sought, to an LSB page.